Xilinx MicroBlaze Reference Manual page 88

The following table summarizes all types of accesses issued by the data cache AXI4
interface.
Table 2-40: Data Cache Interface Accesses
Policy
Write-
through
Write-back
Victim Cache
The victim cache is enabled by setting the parameter
defines the number of cache lines that can be stored in the victim cache. Whenever a
complete cache line is evicted from the cache, it is saved in the victim cache. By saving the
most recent lines they can be fetched much faster, should the processor request them,
thereby improving performance. If the victim cache is not used, all evicted cache lines must
be read from memory again when they are needed.
With the AXI4 interface,
from/to the victim cache each clock cycle, either 32 bits or an entire cache line.
To be able to use the victim cache, write-back must be enabled and area optimization must
Note:
not be enabled.
Data Cache Software Support
MSR Bit
The DCE bit in the MSR controls whether or not the cache is enabled. When disabling
caches the user must ensure that all the prior writes within the cacheable range have been
completed in external memory before reading back over
writing to a semaphore immediately before turning off caches, and then in a loop poll until
it has been written. The contents of the cache are preserved when the cache is disabled.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
State Direction
Cache Read Burst for 32-bit interface non-exclusive access and exclusive
Enabled access with ACE enabled, single access otherwise
Write Single access
Cache Read Burst for 32-bit interface exclusive access with ACE enabled,
Disabled single access otherwise
Write Single access
Cache Read Burst for 32-bit interface, single access otherwise
Enabled
Write Burst for 32-bit interface cache lines with more than one valid
word, a single access otherwise
Cache Read Burst for 32-bit interface non-exclusive access, discarding all but
Disabled the desired data, a single access otherwise
Write Single access
C_DCACHE_DATA_WIDTH
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Access Type
C_DCACHE_VICTIMS
determines the amount of data transferred
. This can be done by
M_AXI_DP
Send Feedback
to 2, 4 or 8. This
88