Xilinx MicroBlaze Reference Manual page 38

X-Ref Target - Figure 2-14
C_ADDR_SIZE = 32 or C_USE_MMU ≠ 3:
0
PAE: C_ADDR_SIZE > 32 and C_USE_MMU = 3 (n = C_ADDR_SIZE):
0
Table 2-20: Translation Look-Aside Buffer Low Register (TLBLO)
1
Bits Name
0:21 RPN
0:n-11
22 EX
n-10
23 WR
n-9
24:27 ZSEL
n-8:n-5
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
RPN
Figure 2-14: TLBLO
Real Page Number or Physical Page Number
When a TLB hit occurs, this field is read from the TLB entry and is
used to form the physical address. Depending on the value of the
SIZE field, some of the RPN bits are not used in the physical address.
Software must clear unused bits in this field to zero.
Only defined when C_USE_MMU=3 (Virtual).
Read/Write
Executable
When bit is set to 1, the page contains executable code, and
instructions can be fetched from the page. When bit is cleared to 0,
instructions cannot be fetched from the page. Attempts to fetch
instructions from a page with a clear EX bit cause an instruction-
storage exception.
Read/Write
Writable
When bit is set to 1, the page is writable and store instructions can
be used to store data at addresses within the page.
When bit is cleared to 0, the page is read-only (not writable).
Attempts to store data into a page with a clear WR bit cause a data
storage exception.
Read/Write
Zone Select
This field selects one of 16 zone fields (Z0-Z15) from the zone-
protection register (ZPR).
For example, if ZSEL 0x5, zone field Z5 is selected. The selected ZPR
field is used to modify the access protection specified by the TLB
entry EX and WR fields. It is also used to prevent access to a page by
overriding the TLB V (valid) field.
Read/Write
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Chapter 2: MicroBlaze Architecture
22 23 24
n-10 n-9 n-8
ZSEL
EX WR
Description
28 29 30 31
n-3 n-2 n-1
n-4
W I M
G
X19751-091317
Reset Value
0x000000
0
0
0x0
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38