Xilinx MicroBlaze Reference Manual page 37

Table 2-19: Zone Protection Register (ZPR)
Bits Name
0:1 ZP0
2:3 ZP1
... ...
30:31 ZP15
Translation Look-Aside Buffer Low Register (TLBLO)
The Translation Look-Aside Buffer Low Register is used to access MMU Unified Translation
Look-Aside Buffer (UTLB) entries. It is controlled by the
MicroBlaze. The register is only implemented if
and
C_AREA_OPTIMIZED
MFS and MTS instructions, the TLBLO is specified by setting Sa = 0x1003.
When reading or writing TLBLO, the UTLB entry indexed by the TLBX register is accessed.
The register is readable according to the memory management special registers parameter
C_MMU_TLB_ACCESS
When the MMU Physical Address Extension (PAE) is enabled (parameters
and
C_ADDR_SIZE
and MTS instructions, and the most significant bits with the MFSE and MTSE instruction.
When writing the register with PAE enabled, the most significant bits must be written first.
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBLO entries).
The UTLB is not reset by the external reset inputs: Reset and Debug_Rst. This means that
Note:
the entire UTLB must be initialized after reset, to avoid any stale data.
The following figure illustrates the TLBLO register and
and reset values. When PAE is enabled the RPN field of the register is extended according
to the
C_ADDR_SIZE
address.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Zone Protect
User mode (MSR[UM] = 1):
00 = Override V in TLB entry. No access to the page is allowed
01 = No override. Use V, WR and EX from TLB entry
10 = No override. Use V, WR and EX from TLB entry
11 = Override WR and EX in TLB entry. Access the page as writable
and executable
Privileged mode (MSR[UM] = 0):
00 = No override. Use V, WR and EX from TLB entry
01 = No override. Use V, WR and EX from TLB entry
10 = Override WR and EX in TLB entry. Access the page as writable
and executable
11 = Override WR and EX in TLB entry. Access the page as writable
and executable
Read/Write
is set to 0 (Performance) or 2 (Frequency). When accessed with the
.
> 32), the 32 least significant bits of TLBLO are accessed with the MFS
parameter up to 54 bits to be able to hold up to a 64-bit physical
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Description
C_USE_MMU
is greater than 1 (User Mode),
C_USE_MMU
Table 2-20
Reset Value
0x00000000
configuration option on
= 3
C_USE_MMU
provides bit descriptions
Send Feedback
37