Xilinx MicroBlaze Reference Manual page 291

Registers Altered
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
• 1 cycle with
• 2 cycles with
Notes
The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions
(C_USE_REORDER_INSTR = 1).
The extended address instruction is only valid if MicroBlaze is configured to use extended address
(C_ADDR_SIZE > 32).
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
292
Send Feedback