Xilinx MicroBlaze Reference Manual page 152

Table 3-6: AXI Interface Signal Definitions (Cont'd)
Interface
M_AXI_DC C_M_AXI_DC_AWCACHE
M_ACE_DC
C_M_AXI_DC_ARPROT
C_M_AXI_DC_AWPROT
C_M_AXI_DC_ARQOS
C_M_AXI_DC_AWQOS
The instruction cache interface (
the MMU physical address extension (PAE) is enabled, depending on the value of the
parameter
C_ADDR_SIZE
The data cache interface (
depending on the value of the parameter C_ADDR_SIZE.
See the AMBA AXI and ACE Protocol Specification (Arm IHI 0022E)
details.
Stream Interfaces
The MicroBlaze AXI4-Stream interfaces (
implemented as 32-bit masters and slaves. See the AMBA 4 AXI4-Stream Protocol
Specification, Version 1.0 (Arm IHI 0051A)
Write Operation
A write to the stream interface is performed by MicroBlaze using one of the put or putd
instructions. A write operation transfers the register contents to an output AXI4 interface.
The transfer is completed in a single clock cycle for blocking mode writes (put and cput
instructions) as long as the interface is not busy. If the interface is busy, the processor stalls
until it becomes available. The non-blocking instructions (with prefix n), always complete in
a single clock cycle even if the interface is busy. If the interface was busy, the write is
inhibited and the carry bit is set in the MSR.
The control instructions (with prefix c) set the AXI4-Stream
used to indicate the boundary of a packet.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Signal
Memory Type, normal access:
• Write-back Read and Write-allocate (1111)
Memory Type, exclusive access:
• Normal Non-cacheable Non-bufferable (0010)
Access Permission:
• Unprivileged, secure data access (000) if input signal
Non_Secure[2] = 0
• Unprivileged, non-secure data access (010) if input signal
Non_Secure[2] = 1
Quality of Service, read access:
• Priority 12 ((1100)
Quality of Service, write access:
• Priority 8 (1000)
) address width can range from 32 - 64 bits when
M_AXI_IC
.
or
M_AXI_DC M_ACE_DC
M0_AXIS
[Ref 14]
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Description
) address width can range from 32 - 64 bits,
[Ref 15]
.. , ..
M15_AXIS S0_AXIS
document for further details.
output, to '1', which is
TLAST
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document for
) are
S15_AXIS
153