Microblaze Core Configurability - Xilinx MicroBlaze Reference Manual

MicroBlaze Core Configurability

The MicroBlaze core has been developed to support a high degree of user configurability.
This allows tailoring of the processor to meet specific cost/performance requirements.
Configuration is done using parameters that typically enable, size, or select certain
processor features. For example, the instruction cache is enabled by setting the
C_USE_ICACHE
range, are all configurable using:
C_ICACHE_HIGHADDR
Parameters valid for the latest version of MicroBlaze are listed in
are recognized by older versions of MicroBlaze; however, the configurability is fully
backward compatible.
Shaded rows indicate that the parameter has a fixed value and cannot be modified.
Note:
Table 3-19: Configuration Parameters
Parameter Name
C_FAMILY
C_DATA_SIZE
C_ADDR_SIZE
C_DYNAMIC_BUS_SIZING
C_SCO
C_AREA_OPTIMIZED
C_OPTIMIZATION
C_INTERCONNECT
C_ENDIANNESS
1
C_BASE_VECTORS
C_FAULT_TOLERANT
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
parameter. The size of the instruction cache, and the cacheable memory
C_CACHE_BYTE_SIZE
respectively.
Feature/Description
Target Family
Data Size
Address Size
Legacy
Xilinx internal
Select implementation
optimization:
0 = Performance
1 = Area
2 = Frequency
Reserved for future use
Select interconnect
2 = AXI4 only
3 = AXI4 and ACE
Select endianness
1 = Little Endian
Configurable base
vectors
Implement fault
tolerance
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Chapter 3: MicroBlaze Signal Interface Description
,
C_ICACHE_BASEADDR
Table
Allowable Default
Values Value
Listed in virtex7
Table 3-20
32 32
32-64 32
1
0
0, 1, 2
0
2, 3
1
0x00000000 0x0000
-0xffffff80 0000
0, 1
, and
3-19. Not all of these
Tool
VHDL Type
Assigned
yes string
NA integer
NA integer
1 NA integer
0 NA integer
0 integer
0 NA integer
2 integer
1 yes integer
std_logic_
vector
yes integer
0
174
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