Xilinx MicroBlaze Reference Manual page 226

fadd Floating-Point Arithmetic Add
rD, rA, rB
fadd
0 1 0 1 1 0
0
6
Description
The floating-point sum of registers rA and rB, is placed into register rD.
Pseudocode
if isDnz(rA) or isDnz(rB) then
←
(rD) 0xFFC00000
←
FSR[DO]
←
ESR[EC]
else if isSigNaN(rA) or isSigNaN(rB)or
(isPosInfinite(rA) and isNegInfinite(rB)) or
(isNegInfinite(rA) and isPosInfinite(rB))) then
←
(rD) 0xFFC00000
←
FSR[IO]
←
ESR[EC]
else if isQuietNaN(rA) or isQuietNaN(rB) then
←
(rD) 0xFFC00000
else if isDnz((rA)+(rB)) then
←
(rD) signZero((rA)+(rB))
←
FSR[UF]
←
ESR[EC]
else if isNaN((rA)+(rB)) then
←
(rD) signInfinite((rA)+(rB))
←
FSR[OF]
←
ESR[EC]
else
←
(rD) (rA) + (rB)
Registers Altered
• rD, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
• FSR[IO,UF,OF,DO]
Latency
• 4 cycles with
• 6 cycles with
• 1 cycle with
Note
This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Add
rD rA
11
1
00110
1
00110
1
00110
1
00110
=0
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
=2
C_AREA_OPTIMIZED
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
16 21 31
227
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