Xilinx MicroBlaze Reference Manual page 147

Hardware Controlled
When the
Pause
accesses, the pipeline is halted and the
external hardware that it is safe to perform actions such as stopping the clock, resetting the
processor or other IP cores. To continue from pause, the input signal
to zero. In this case MicroBlaze continues instruction execution where it was previously
paused.
The
Dbg_Continue
processor to continue from pause. External hardware should handle this signal and clear
pause after performing any other necessary hardware actions such as starting the clock.
After external hardware has set or cleared Pause, it is recommended to wait until
is set or cleared before Pause is changed again, to avoid any issues due to
Pause_Ack
incorrectly detected pause acknowledge.
All signals used for hardware control (
synchronous to the MicroBlaze clock.
The block diagram in
processor and how to implement clock control. In this example,
hardware signal that pauses processor execution and stops the clock. When
cleared to zero, the clock is enabled and execution resumes. This example assumes that the
external logic monitors
X-Ref Target - Figure 3-3
Clock Control
Clock
Utility Vector Logic
Pause
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
input signal is set to one and MicroBlaze has completed all external
output signal from MicroBlaze indicates that the debugger requests the
Pause
Figure 3-3 illustrates how to use the pause functionality to halt the
, and clears
Dbg_Continue
Binary Counter
Utility Buffer
CLK
Q[0:0]
SCLR
BUFGCE
LOAD
L[0:0]
Figure 3-3: Pause Clock Control Block Diagram
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Chapter 3: MicroBlaze Signal Interface Description
output signal is set. This indicates to
Pause_Ack
, , and
Pause_Ack
to allow debugging.
Pause
MicroBlaze
Clk
Pause
Dbg_Continue
C_ENABLE_DISCRETE_PORTS = 1
must be cleared
Pause
) are
Dbg_Continue
is an external
Pause
is
Pause
Pause_Ack
Dbg_Continue
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