Xilinx MicroBlaze Reference Manual page 183

Table 3-19: Configuration Parameters (Cont'd)
Parameter Name
C_M_AXI_IC_ARUSER_WIDTH
C_M_AXI_IC_WUSER_WIDTH
C_M_AXI_IC_RUSER_WIDTH
C_M_AXI_IC_BUSER_WIDTH
C_M_AXI_IC_USER_VALUE
C_STREAM_INTERCONNECT
C_Mn_AXIS_PROTOCOL
C_Sn_AXIS_PROTOCOL
C_Mn_AXIS_DATA_WIDTH
C_Sn_AXIS_DATA_WIDTH
C_NUM_SYNC_FF_CLK
C_NUM_SYNC_FF_CLK_IRQ
C_NUM_SYNC_FF_CLK_DEBUG
C_NUM_SYNC_FF_DBG_CLK
C_NUM_SYNC_FF_DBG_TRACE_CLK
1. The 7 least significant bits must all be 0.
2. Not all sizes are permitted in all architectures. The cache uses 0 - 32 RAMB primitives (0 if cache size is less than 2048).
3. Not available when
C_AREA_OPTIMIZED
1.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user width
Instruction cache AXI
user value
Select AXI4-Stream
interconnect
AXI4-Stream protocol
AXI4-Stream protocol
AXI4-Stream master
data width
AXI4-Stream slave data
width
Reset and Wakeup[0:1]
synchronization stages
Interrupt input signal
synchronization stages
Dbg_ serial signal
synchronization stages
Internal synchronization
stages to Dbg_Clk
Internal synchronization
stages to Dbg_Trace_Clk
is set to 1 (Area).
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Allowable Default Tool
Values Value Assigned
5 5
1 1
1 1
1 1
0-31 31
0,1 0
GENERIC GENERIC
GENERIC GENERIC
32 32
32 32
0- 2
0- 1
0- 2
0- 1
0- 1
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VHDL Type
integer
integer
integer
integer
integer
integer
string
string
integer
NA
integer
NA
integer
integer
integer
integer
integer
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