Xilinx MicroBlaze Reference Manual page 77

Equivalent Pseudocode
←
ESR[DS]
if ESR[DS] then
←
BTR branch target PC
if MMU exception then
if branch preceded by IMM then
r17
else
r17
else
r17
else if MMU exception then
if instruction preceded by IMM then
←
r17
else
←
r17
else
←
r17 PC + 4
←
PC C_BASE_VECTORS + 0x00000020
←
MSR[EE]
←
MSR[UMS]
←
ESR[EC]
←
ESR[ESS]
←
EAR exception specific value
←
FSR exception specific value
Reservation
Breaks
There are two kinds of breaks:
• Hardware (external) breaks
• Software (internal) breaks
Hardware Breaks
Hardware breaks are performed by asserting the external break signal (that is, the
and
Ext_NM_BRK
while the instruction in the decode stage is replaced by a branch to the break vector
(address
C_BASE_VECTORS
The break return address (the PC associated with the instruction in the decode stage at the
time of the break) is automatically loaded into general purpose register R16. MicroBlaze
also sets the Break In Progress (
A normal hardware break (that is, the
and MSR[EIP] are set to 0 (that is, there is no break or exception in progress). The Break In
Progress flag disables interrupts. A non-maskable break (that is, the
port) is always handled immediately.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
exception in delay slot
←
PC - 8
←
PC - 4
←
invalid value
PC - 4
PC
←
0, MSR[EIP] 1
←
MSR[UM], MSR[UM]
exception specific value
exception specific value
←
0
input ports). On a break, the instruction in the execution stage completes
+ 0x18).
) flag in the Machine Status Register (MSR).
BIP
www.xilinx.com
Chapter 2: MicroBlaze Architecture
←
0, MSR[VMS] MSR[VM], MSR[VM]
input port) is only handled when MSR[BIP]
Ext_BRK
←
0
Ext_BRK
input
Ext_NM_BRK
77
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