Xilinx MicroBlaze Reference Manual page 241

lbu Load Byte Unsigned
rD, rA, rB
lbu
lbur rD, rA, rB
rD, rA, rB
lbuea
1 1 0 0 0 0
0
6
Description
Loads a byte (8 bits) from the memory location that results from adding the contents of registers rA
and rB. The data is placed in the least significant byte of register rD and the other three bytes in rD are
cleared.
If the R bit is set, a byte reversed memory location is used, loading data with the opposite endianness
of the endianness defined by the E bit (if virtual protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding
them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This
only applies to accesses with user mode and virtual protected mode enabled.
A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled,
and the instruction is not explicitly allowed.
Pseudocode
if EA = 1 then
← (
Addr rA) & (rB)
else
← (
Addr rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC] 10010;ESR[S]
←
MSR[UMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else
(rD)[24:31]
(rD)[0:23]
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
←
0
←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 0; ESR[DIZ]
←
MSR[UM]; MSR[VMS] MSR[VM]; MSR[UM]
←
Mem(Addr)
←
0
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 R 0 EA 0 0 0 0 0 0 0
16 21
←
MSR[VM]; MSR[UM] 0; MSR[VM]
←
1
←
0; MSR[VM]
31
←
0
←
0
242
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