Xilinx MicroBlaze Reference Manual page 251

Registers Altered
• rD and MSR[C], unless an exception is generated, in which case they are unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
Latency
• 1 cycle with
• 2 cycles with
Notes
This instruction is used together with SWX to implement exclusive access, such as semaphores and
spinlocks.
The carry flag (MSR[C]) might not be set immediately (dependent on pipeline stall behavior). The LWX
instruction should not be immediately followed by an MSRCLR, MSRSET, MTS, or SRC instruction, to
ensure the correct value of the carry flag is obtained.
mbar Memory Barrier
IMM
mbar
1 0 1 1 1 0
0
6
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
Memory Barrier
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
IMM
11
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
16 31
252
Send Feedback