Xilinx MicroBlaze Reference Manual page 39

Table 2-20: Translation Look-Aside Buffer Low Register (TLBLO) (Cont'd)
1
Bits Name
28 W
n-4
29 I
n-3
30 M
n-2
31 G
n-1
1. The bit index n =
Translation Look-Aside Buffer High Register (TLBHI)
The Translation Look-Aside Buffer High Register is used to access MMU Unified Translation
Look-Aside Buffer (UTLB) entries. It is controlled by the
MicroBlaze. The register is only implemented if
and
C_AREA_OPTIMIZED
MFS and MTS instructions, the TLBHI is specified by setting Sa = 0x1004. When reading or
writing TLBHI, the UTLB entry indexed by the TLBX register is accessed.
The register is readable according to the memory management special registers parameter
C_MMU_TLB_ACCESS
PID is also used when accessing a TLB entry:
• When writing TLBHI the value of PID is stored in the TID field of the TLB entry
• When reading TLBHI and MSR[UM] is not set, the value in the TID field is stored in PID
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBHI entries).
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Write Through
When the parameter C_DCACHE_USE_WRITEBACK is set to 1, this
bit controls caching policy. A write-through policy is selected when
set to 1, and a write-back policy is selected otherwise.
This bit is fixed to 1, and write-through is always used, when
C_DCACHE_USE_WRITEBACK is cleared to 0.
Read/Write
Inhibit Caching
When bit is set to 1, accesses to the page are not cached (caching is
inhibited).
When cleared to 0, accesses to the page are cacheable.
Read/Write
Memory Coherent
This bit is fixed to 0, because memory coherence is not implemented
on MicroBlaze.
Read Only
Guarded
When bit is set to 1, speculative page accesses are not allowed
(memory is guarded).
When cleared to 0, speculative page accesses are allowed.
The G attribute can be used to protect memory-mapped I/O devices
from inappropriate instruction accesses.
Read/Write
applies when PAE is enabled.
C_ADDR_SIZE
is set to 0 (Performance) or 2 (Frequency). When accessed with the
.
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Chapter 2: MicroBlaze Architecture
Description
C_USE_MMU
is greater than 1 (User Mode),
C_USE_MMU
Reset Value
0/1
0
0
0
configuration option on
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