Xilinx MicroBlaze Reference Manual page 171

Table 3-16: MicroBlaze Trace Signals (Cont'd)
Signal Name
1
Trace_Data_Read
1
Trace_Data_Write
Trace_DCache_Req
Trace_DCache_Hit
Trace_DCache_Rdy
Trace_DCache_Read
Trace_ICache_Req
Trace_ICache_Hit
Trace_ICache_Rdy
Trace_OF_PipeRun
3
Trace_EX_PipeRun
3
Trace_MEM_PipeRun
Trace_MB_Halted
1. Valid only when
Trace_Valid_Instr
2. Valid only when
Trace_Exception_Taken
3. Not used with area optimization feature
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Description
D-side memory access is a read
D-side memory access is a write
Data memory address is within
D-Cache range. Set when a memory
access instruction is executed.
Data memory address is present in
D-Cache. Set simultaneously with
Trace_DCache_Req when a cache hit
occurs.
Data memory address is within
D-Cache range and the access is
completed. Only set following a request
with Trace_DCache_Req = 1 and
Trace_DCache_Hit = 0.
The D-Cache request is a read. Valid
only when Trace_DCache_Req = 1.
Instruction memory address is within
I-Cache range, and the cache is enabled
in the Machine Status Register. Set
when an instruction is read into the
instruction prefetch buffer.
Instruction memory address is present
in I-Cache. Set simultaneously with
Trace_ICache_Req when a cache hit
occurs.
• Instruction memory address is present
in I-Cache. Set simultaneously with
Trace_ICache_Req when a cache hit
occurs in this case.
• Instruction memory address is within
I-Cache range and the access is
completed. Set following a request
with Trace_ICache_Req = 1 and
Trace_ICache_Hit = 0 in this case.
Pipeline advance for Decode stage
Pipeline advance for Execution stage
Pipeline advance for Memory stage
Pipeline is halted by debug
= 1
= 1
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VHDL Type Direction
std_logic output
output
std_logic
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
std_logic output
output
std_logic
std_logic output
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