Xilinx MicroBlaze Reference Manual page 66

The following figure diagrams the general process for examining a TLB entry.
X-Ref Target - Figure 2-21
TLBHI[TAG] with EA[EPN]
Using TLBHI[SIZE]
Match (TLB Hit)
Check Access
Data Reference
Read TLBLO[RPN]
Using TLBHI[SIZE]
Extract Offset from EA
using TLBHI[SIZE]
The following sections describe the conditions under which exceptions occur due to TLB
access failures.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Check TLB-Entry
Using Virtual Address
No
TLB HI[V]=1
Yes
TLBHI[TID]=0x00
Yes No
Match
Compare
No Match
Not allowed
Allowed
Instruction Fetch
Check for
Guarded Storage
Not Guarded
Figure 2-21: General Process for Examining a TLB Entry
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Chapter 2: MicroBlaze Architecture
Compare
No Match
TLBHI[TID] with PID
Guarded
Generate Physical Address from
TLB Entry Miss
TLB Entry Miss
TLB Entry Miss
Access Violation
Storage Violation
TLBLO[RPN] and Offset
X19758-091317
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