Xilinx MicroBlaze Reference Manual page 130

After a MicroBlaze core has invalidated one or more entries, it must execute a memory
barrier instruction (MBAR), to ensure that all peer processors have completed their TLB
invalidation.
• Branch Target Cache invalidation: When a MicroBlaze core in the coherency domain
invalidates the Branch Target Cache, either with a memory barrier instruction or with a
synchronizing branch, hardware messages ensure that all other cores in the coherency
domain will do the same.
In particular, this means that self-modifying code can be used transparently within the
coherency domain in a multi-processor system, provided that the guidelines in
modifying Code
Protocol Compliance
The MicroBlaze instruction cache interface issues the following subset of the possible ACE
transactions:
• ReadClean: Issued when a cache line is allocated.
• ReadOnce: Issued when the cache is off, or if the MMU Inhibit Caching bit is set for the
cache line.
The MicroBlaze data cache interface issues the following subset of the possible ACE
transactions:
• ReadClean: Issued when a cache line is allocated.
• CleanUnique: Issued when an SWX instruction is executed as part of an exclusive access
sequence.
• ReadOnce: Issued when the cache is off, or if the MMU Inhibit Caching bit is set for the
cache line.
• WriteUnique: Issued whenever a store instruction performs a write.
• CleanInvalid: Issued when a
• MakeInvalid: Issued when a
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
are followed.
WDC.EXT.FLUSH
WDC.EXT.CLEAR
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Chapter 2: MicroBlaze Architecture
instruction is executed.
instruction is executed.
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