Xilinx IBERT ML628 Getting Started Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Computer Hardware
  5. ML628
  6. Getting started manual
Xilinx IBERT ML628 Getting Started Manual

Xilinx IBERT ML628 Getting Started Manual

Hide thumbs Also See for IBERT ML628:
Table of Contents

Advertisement

Quick Links

Download this manual
ML628 IBERT
Getting Started Guide
(ISE 13.1)
UG806 (v1.0) May 20, 2011

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the IBERT ML628 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Xilinx IBERT ML628

Summary of Contents for Xilinx IBERT ML628

  • Page 1 ML628 IBERT Getting Started Guide (ISE 13.1) UG806 (v1.0) May 20, 2011...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Table Of Contents

    ........... 36 ibert_v6_qxxx_top.ucf ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 4 ..............51 www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 5: Chapter 1: Ml628 Ibert Getting Started Guide

    Board. Extracting the Project Files. Connecting the GTX Transceivers and Reference Clocks. Configuring the FPGA. Setting Up the ChipScope Pro Software. Viewing GTX Transceiver Operation. Closing the IBERT Demonstration. ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 6: Requirements

    The hardware and software required to rebuild the IBERT demonstration designs are: • Xilinx ISE® Design Suite version 13.1 or higher • PC with a version of the Windows operating system supported by Xilinx ISE Design Suite • ML628 IBERT demonstration design source files (provided online as collection rdf0117_13-1.zip) at:...

  • Page 7: Extracting The Project Files

    CF card labeled IBERT #1. They are also available online along with .bit files for all 16 designs (as collection rdf0116_13-1.zip) at: http://www.xilinx.com/products/boards/ml628/reference_designs.htm ml628_cpj.zip contains two project files: ml628_gth.cpj and ml628_gtx.cpj. These files are used to load pre-saved MGT/IBERT and SuperClock-2 module control settings for the GTH and GTX demonstrations.
  • Page 8 Figure 1-2 shows the connector pinout. X-Ref Target - Figure 1-2 GTH Connector Pad GTH Connector Pinout UG806_c1_02_041411 Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 9: Attach The Gth Quad Connector

    Hold the connector flush with the board and fasten it by tightening the two captive screws. X-Ref Target - Figure 1-4 UG806_c1_04_022411 Figure 1-4: BullsEye Connector Attached to Quad 117 ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 10: Gth Transceiver Clock Connections

    X-Ref Target - Figure 1-5 UG806_c1_05_022411 Figure 1-5: SMA F-F Adapter X-Ref Target - Figure 1-6 TX Coax SMA F-F Adapter RX Coax UG806_c1_06_022811 Figure 1-6: TX-To-RX Loopback Connection Example www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 11: Configuring The Fpga

    The FPGA can also be configured through ChipScope Pro or iMPACT software using the .bit files which are available online (as collection rdf0116_13-1.zip) at: http://www.xilinx.com/products/boards/ml628/reference_designs.htm To configure from the CF card: Insert the CF card labeled IBERT #1 into the CF card reader slot located on the bottom-side (upper-right corner) of the board.
  • Page 12 GTX Quad 104 GTX Quad 105 IBERT #2 GTX Quad 112 GTX Quad 113 GTX Quad 114 GTX Quad 115 Place the main power switch SW1 to the ON position. www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 13: Setting Up The Chipscope Pro Software

    The .cpj file loads pre-saved project settings for the demonstration including MGT/ IBERT and clock module control parameters. For more information regarding MGT/ IBERT settings, refer to www.xilinx.com/support/documentation/sw_manuals/ xilinx13_1/chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores. Click the Open Cable button (Figure 1-9).
  • Page 14 This is a limitation of the GTH IBERT core only. It does not exist in the GTX IBERT core. X-Ref Target - Figure 1-11 ug806_c1_11_041411 Figure 1-11: GTH IBERT 2.03a with No Reference Clock www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 15: Starting The Superclock-2 Module

    Si570 ROM Addr) are preset to 44 to produce an output frequency of 174.69 MHz. Entering a different ROM address changes the reference clock(s) frequency. The complete list of pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in Table 1-2, page ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 16 GTH IBERT demonstration design. Restart the ChipScope application and select File → Open Project. When the Open Project window appears, select ml628_gth.cpj and click Open. Click the Open Cable button (Figure 1-15). www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 17 Restarting the SuperClock-2 module is not required. The Si5268 clock outputs will be enabled and running at the correct frequency. X-Ref Target - Figure 1-16 ug806_c1_16_041411 Figure 1-16: IBERT V6GTH Project Settings ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 18: Viewing Gth Transceiver Operation

    The GTX transmitter differential output swing is preset to 800 mV. • Verify that there are no bit errors. If the count is not zero, see In Case of RX Bit Errors. www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 19: In Case Of Rx Bit Errors

    The GTH receiver analog front end (AFE) does not support DC coupling (see UG371, Virtex-6 FPGA GTH Transceivers User Guide for details). For this reason, a DC component in ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 20: Closing The Ibert Demonstration

    Place the main power switch SW1 in the off position. More Information Additional information on the ChipScope Pro software and GTH IBERT core can be found • www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores • http://www.xilinx.com/support/documentation/ip_documentation/ chipscope_ibert_virtex6_gth.pdf, DS755 - ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-6 GTH.
  • Page 21 Figure 1-23 shows the connector pinout. X-Ref Target - Figure 1-23 GTX Connector Pad GTX Connector Pinout UG806_c1_23_041411 Figure 1-23: A – GTX Connector Pad. B – GTX Connector Pinout ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 22: Attach The Gtx Quad Connector

    Figure 1-26 and detailed below: TX0_P → SMA F-F Adapter → RX0_P • TX0_N → SMA F-F Adapter → RX0_N • TX1_P → SMA F-F Adapter → RX1_P • www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 23 X-Ref Target - Figure 1-25 UG806_c1_25_041411 Figure 1-25: SMA F-F Adapter X-Ref Target - Figure 1-26 TX Coax SMA F-F Adapter RX Coax UG806_c1_26_041411 Figure 1-26: TX-To-RX Loopback Connection Example ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 24: Configuring The Fpga

    The FPGA can also be configured through ChipScope Pro or iMPACT software using the .bit files which are available online (as collection rdf0116_13-1.zip) at: http://www.xilinx.com/products/boards/ml628/reference_designs.htm To configure from the CF card: Insert the CF card labeled IBERT #2 into the CF card reader slot located on the bottom-side (upper-right corner) of the board.

  • Page 25: Setting Up The Chipscope Pro Software

    (.cpj) were extracted. Select ml628_gtx.cpj and click Open. Note: The .cpj file loads pre-saved project settings for the demonstration including MGT/IBERT and clock module control parameters. For more information regarding MGT/IBERT settings, refer www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores. ML628 IBERT Getting Started Guide www.xilinx.com...

  • Page 26: Starting The Superclock-2 Module

    1) An always-on Si570 crystal oscillator and, 2) an Si5386 jitter-attenuating clock multiplier. Outputs from either device can be used to drive the transceiver reference clocks. To start the SuperClock-2 Module: www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 27 X-Ref Target - Figure 1-32 The ROM address value for the Si5368 clock multiplier is preset to 2 (162.690 MHz) Si5358 start button UG806_c1_32_041411 Figure 1-32: Si5368 Address, Frequency and Start Button ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 28: Viewing Gtx Transceiver Operation

    The line rate for all four GTX transceivers is 6.5 Gps (see MGT Link Status in Figure 1-35). • The GTX transmitter differential output swing is preset to 590 mV. • Verify that there are no bit errors. www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 29: Closing The Ibert Demonstration

    Figure 1-35: GTX IBERT Console Additional information on the ChipScope Pro software and IBERT core can be found in: • www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores • http://www.xilinx.com/support/documentation/ip_documentation/ chipscope_ibert_virtex6_gth.pdf, DS755 - ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-6 GTH.

  • Page 30: More Information

    Place the main power switch SW1 in the off position. More Information Additional information on the ChipScope Pro software and GTH IBERT core can be found • www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores • http://www.xilinx.com/support/documentation/ip_documentation/ chipscope_ibert_virtex6_gtx.pdf, DS732 - ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-6 GTX.

  • Page 31: Superclock-2 Frequency Table

    Interlaken 265.625 594.000 Generic 275.000 Interlaken 390.625 SMPTE435M 167.063 Generic 280.000 Interlaken 531.250 SMPTE435M 334.125 Generic 285.000 OBSAI 76.800 SMPTE435M 668.250 Generic 290.000 OBSAI 153.600 XAUI 78.125 Generic 295.000 ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...

  • Page 32: Ibert Demonstration Designs

    Source Directories and Files The file rdf0116_13-1.zip contains the source files for 16 individual designs (one for each GTH and GTX Quad on the ML628 board). The .zip file is located at: http://www.xilinx.com/products/boards/ml628/reference_designs.htm. Each design is saved in a separate directory: ML628_gth_q106/...

  • Page 33: Ibert Design Files

    ChipScope or iMPACT and a JTAG download cable. example_implement_ibert_v6_q1xx.prj The example_implement_ibert_v6_q1xx.prj project file is used with the Xilinx Synthesis Technology (xst) synthesis application to provide a list of files associated with the design. The .prj file contains the language, library name (e.g., "work") and the design files.

  • Page 34: Example_Implement_Ibert_V6_Q1Xx.xst

    IBERT Demonstration Designs For additional details on this file, see: • http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst.pdf, UG627 - XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices example_implement_ibert_v6_q1xx.xst The example_implement_ibert_v6_q1xx.xst file contains the arguments that are passed to the xst synthesis application when the application is run in command line (i.e., script) mode.

  • Page 35: Vio_V6_Si84_So78.Ngc

    IBERT Demonstration Designs • www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores vio_v6_si84_so78.ngc The vio_v6_si84_so78.ngc file is a binary implementation netlist file containing the logic and constraints required to implement the ChipScope Virtual Input/Output (VIO) core in an FPGA. vio_v6_si84_so78.ngc is created using the ISE Design Suite CORE Generator.

  • Page 36: I2C_Sclk2_Control_Bb

    CORE Generator during the IBERT core generation, but is modified to include the system clock, I C and SuperClock-2 control pin mapping. For additional details on the user constrains file, refer to: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf, UG625 - Constraints Guide. vio_sclk2_control.v The vio_sclk2_control.v file provides the interface between the ChipScope Virtual IO (VIO) and the SuperClock-2 control module, i2c_sclk2_control.ngc.
  • Page 37 Device: xc6vhx380t • Package: ff1923 • Speed Grade: -2 Figure 1-37 shows the correct settings. X-Ref Target - Figure 1-37 UG806_c1_37_041411 Figure 1-37: CORE Generator Project Options (Part Options) ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 38 Click OK to close the Project Options window. In the IP Catalog pane of the CORE Generator window (Figure 1-39) select: Debug & Verification → ChipScope Pro → IBERT Virtex6 GTH (ChipScope Pro - IBERT) 2.03.a www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 39 • Add RXUSERCLK probe: unchecked • GTH Naming Style: MGT m n • MGT Column: Right • Frequency: 25 MHz • Pin Location: UNASSIGNED • Pin Input Standard: LVCMOS25 ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 40 1-41, then click Next: • Protocol: OTU4 • Refclk (MHz): 174.69 • GTH count: 4 X-Ref Target - Figure 1-41 UG806_c1_41_050411 Figure 1-41: CORE Generator - IBERT GTH Customization - Page 2 www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 41 12. Enter the information shown here and in Figure 1-43, then click Next: • Quad_117: MGTREFCLK 117 X-Ref Target - Figure 1-43 UG806_c1_43_050411 Figure 1-43: CORE Generator - IBERT GTH Customization - Page 4 ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 42 Compare the .v and .ucf files generated here with the identically named source files provided with the ML628 board (see Source Directories and Files, page 32) for details on how the SuperClock-2 control module is integrated and the system clock is connected. www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 43: Creating The Gtx Ibert Core

    GTX Quads with any supported line rate can be created following the same series of steps. For more details on generating IBERT cores, refer to www.xilinx.com/support/ documentation/sw_manuals/xilinx13_1/chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores Start the CORE Generator tool from either the ISE Project Navigator window or a command line: From the Project Navigator window, select: Tools →...
  • Page 44 Device: xc6vhx380t • Package: ff1923 • Speed Grade: -2 Figure 1-37 shows the correct settings. X-Ref Target - Figure 1-47 UG806_c1_47_041411 Figure 1-47: CORE Generator Project Options (Part Options) www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 45 Click OK to close the Project Options window. In the IP Catalog pane of the CORE Generator window (Figure 1-49) select: Debug & Verification → ChipScope Pro → IBERT Virtex6 GTX (ChipScope Pro - IBERT) 2.05.a ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 46 GTX Naming Style: MGT m n • GTX Column: Left • Use External clock source: checked • Frequency: 25 MHz • Pin Location: UNASSIGNED • Pin Input Standard: LVCMOS25 www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 47 Max Rate (Gps): 6.5 • Refclk (MHz): 162.50 • GTH count: 4 X-Ref Target - Figure 1-51 UG806_c1_51_041411 Figure 1-51: CORE Generator - IBERT GTX Customization - Page 2 ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 48 13. Enter the information shown here and in Figure 1-52, then click Next: • MGT0_100: MGTREFCLK0 100 • MGT1_100: MGTREFCLK0 100 • MGT2_100: MGTREFCLK1 100 • MGT3_100: MGTREFCLK1 100 www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...
  • Page 49 Figure 1-54: CORE Generator - IBERT GTX Customization - Page 6 15. The generation process will take a few minutes. When complete, a Readme window will appear (Figure 1-55). Review the information presented and locate the following files: ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011...
  • Page 50 32) for details on how the SuperClock-2 control module is integrated and the system clock is connected. X-Ref Target - Figure 1-55 UG806_c1_55_041411 Figure 1-55: CORE Generator - Readme www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

  • Page 51: Warranty

    For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products. The availability of replacement products is subject to product discontinuation policies at Xilinx.
  • Page 52 Warranty www.xilinx.com ML628 IBERT Getting Started Guide UG806 (v1.0) May 20, 2011...

Table of Contents