Xilinx MicroBlaze Reference Manual page 65

combination. However, this is considered a programming error and results in undefined
behavior.
When a hit occurs, the MMU reads the RPN field from the corresponding TLB entry. Some
or all of the bits in this field are used, depending on the value of the
Table 2-38).
For example, with PAE disabled, if the
represents the physical page number and is used to form the physical address. RPN[14:21]
is not used, and software must clear those bits to 0 when initializing the TLB entry. The
remainder of the physical address is taken from the page-offset portion of the EA. If the
page size is 256 kB, the 32-bit physical address is formed by concatenating RPN[0:13] with
bits 14:31 of the effective address.
Instead, with PAE enabled and assuming a physical address size of 40 bits (
to 40), RPN[0:21] represents the physical page number and RPN[22:29] is not used. The 40-
bit physical address is formed by concatenating RPN[0:21] with bits 14:31 of the effective
address.
Prior to accessing physical memory, the MMU examines the TLB-entry access-control fields.
These fields indicate whether the currently executing program is allowed to perform the
requested memory access.
If access is allowed, the MMU checks the storage-attribute fields to determine how to
access the page. The storage-attribute fields specify the caching policy for memory
accesses.
TLB Access Failures
A TLB-access failure causes an exception to occur. This interrupts execution of the
instruction that caused the failure and transfers control to an interrupt handler to resolve
the failure. A TLB access can fail for two reasons:
• A matching TLB entry was not found, resulting in a TLB miss
• A matching TLB entry was found, but access to the page was prevented by either the
storage attributes or zone protection
When an interrupt occurs, the processor enters real mode by clearing MSR[VM] to 0. In real
mode, all address translation and memory-protection checks performed by the MMU are
disabled. After system software initializes the UTLB with page-translation entries,
management of the MicroBlaze UTLB is usually performed using interrupt handlers running
in real mode.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
field specifies a 256 kB page size, RPN[0:13]
SIZE
www.xilinx.com
Chapter 2: MicroBlaze Architecture
field (see
SIZE
C_ADDR_SIZE
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