Error Detection - Xilinx MicroBlaze Reference Manual

The outputs from the master MicroBlaze core drive the peripherals in the system. All data
leaving the protected area pass through inhibitors. Each inhibitor is controlled from its
associated comparator.
Each protected area of the design must be implemented in its own partition, using a
hierarchical single chip cryptography (SCC) flow. A detailed explanation of this flow, and
further references, can be found in the document Hierarchical Design Methodology Guide
(UG748) [Ref 8].
A block diagram of the system is shown in the following figure.
X-Ref Target - Figure 2-41
MicroBlaze Partition
DLMB
Bram Controller
BRAM
ILMB
Bram Controller
MicroBlaze
Debug Module
MicroBlaze Partition
DLMB
Bram Controller
BRAM
ILMB
Bram Controller
Debug interface – Removed for Production

Error Detection

The error detection use case requires that all transient and permanent faults are detected.
This is essential in fail safe and fault tolerant applications, where redundancy is utilized to
improve system availability.
In this system two redundant MicroBlaze processors run in lockstep. A comparator is used
to signal an error when a mis-match is detected on the outputs of the two processors. Any
error immediately causes both processors to halt, preventing further error propagation.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
C_LOCKSTEP_SLAVE=0
MicroBlaze
Master
Lockstep_Out
Debug
Lockstep_Master_Out
Lockstep_Slave_In
Debug
MicroBlaze
Slave
Lockstep_Out
C_LOCKSTEP_SLAVE=1
Figure 2-41: Lockstep Tamper Protection Application
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Outputs
Inputs
Comparator Partition
Comparator
Inputs
Comparator Partition
Comparator
Peripheral
Partition
I/O Interfaces
External
Memory
Interfaces
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