Xilinx MicroBlaze Reference Manual page 17

Table 2-6: MicroBlaze Instruction Set Summary (Cont'd)
Type A
Type B
SEXT8 Rd,Ra 100100
SEXT16 Rd,Ra 100100
CLZ Rd, Ra 100100
SWAPB Rd, Ra 100100
SWAPH Rd, Ra 100100
WIC Ra,Rb 100100
WDC Ra,Rb 100100
WDC.FLUSH Ra,Rb 100100
WDC.CLEAR Ra,Rb 100100
WDC.CLEAR.EA 100100
Ra,Rb
MTS Sd,Ra 100101
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
0-5 6-10 11-15 16-20
0-5 6-10 11-15
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
00000 Ra
00000 Ra
00000 Ra
00000 Ra
00000 Ra
00000 Ra
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Chapter 2: MicroBlaze Architecture
21-31
16-31
0000000001100000 Rd := s(Ra[24:31])
0000000001100001 Rd := s(Ra[16:31])
0000000011100000 Rd = clz(Ra)
0000000111100000 Rd = (Ra)[24:31, 16:23, 8:15, 0:7]
0000000111100010 Rd = (Ra)[16:31, 0:15]
Rb 00001101000 ICache_Line[Ra >> 4].Tag := 0 if
( C_ICACHE_LINE_LEN = 4 )
ICache_Line[Ra >> 5].Tag := 0 if
( C_ICACHE_LINE_LEN = 8 )
ICache_Line[Ra >> 6].Tag := 0 if
( C_ICACHE_LINE_LEN = 16 )
Rb 00001100100 Cache line is cleared, discarding
stored data.
DCache_Line [Ra >> 4].Tag := 0 if
( C_DCACHE_LINE_LEN = 4 )
DCache_Line[Ra >> 5].Tag := 0 if
( C_DCACHE_LINE_LEN = 8 )
DCache_Line[Ra >> 6].Tag := 0 if
( C_DCACHE_LINE_LEN = 16 )
Rb 00001110100 Cache line is flushed, writing stored
data to memory, and then cleared.
Used when
C_DCACHE_USE_WRITEBACK = 1 .
Rb 00001100110 Cache line with matching address is
cleared, discarding stored data. Used
when
C_DCACHE_USE_WRITEBACK = 1 .
Rb 00011100110 Cache line with matching extended
address Ra & Rb is cleared. Used
when
C_DCACHE_USE_WRITEBACK = 1 .
11 & Sd SPR[Sd] := Ra, where:
· SPR[0x0001] is MSR
· SPR[0x0007] is FSR
· SPR[0x0800] is SLR
· SPR[0x0802] is SHR
· SPR[0x1000] is PID
· SPR[0x1001] is ZPR
· SPR[0x1002] is TLBX
· SPR[0x1003] is TLBLO[LSH]
· SPR[0x1004] is TLBHI
· SPR[0x1005] is TLBSX
Semantics
17
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