Xilinx MicroBlaze Reference Manual page 143

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
3
Dbg_Intr
3
MB_Error
3
Sleep
3
Hibernate
3
Suspend
3
Wakeup[0:1]
3
Dbg_Wakeup
3
Pause
3
Pause_Ack
3
Dbg_Continue
3
Non_Secure[0:3]
Lockstep_...
Dbg_...
Trace_...
1. Only used with
C_USE_INTERRUPT
2. MicroBlaze is a synchronous design clocked with the Clk signal, except for serial hardware debug logic, which is clocked with
the signal. If serial hardware debug logic is not used, there is no minimum frequency limit for
Dbg_Clk
serial hardware debug logic is used, there are signals transferred between the two clock regions. In this case
a higher frequency than
Dbg_Clk
3. Only visible when
C_ENABLE_DISCRETE_PORTS
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Interface I/O
Core O Debug interrupt output, set when a Performance Monitor counter
overflows, available when
(Extended).
Core O Pipeline is halted due to a missed exception, when
C_FAULT_TOLERANT is set to 1.
Core O MicroBlaze is in sleep mode after executing a
or by setting Reset_Mode[0:1] to 10, all external accesses are
completed, and the pipeline is halted.
Core O MicroBlaze is in sleep mode after executing a HIBERNATE
instruction, all external accesses are completed, and the pipeline
is halted.
Core O MicroBlaze is in sleep mode after executing a
instruction, all external accesses are completed, and the pipeline
is halted.
Core I Wake MicroBlaze from sleep mode when either or both bits are
set to 1. Ignored if MicroBlaze is not in sleep mode. The signals
are individually synchronized to Clk according to the parameter
C_ASYNC_WAKEUP[0:1] .
Debug request that external logic should wake MicroBlaze from
Core O
sleep mode with the
Synchronous to Dbg_Update.
Core I When this signal is set MicroBlaze pipeline will be paused after
completing all ongoing bus accesses, and the
will be set. When this signal is cleared again MicroBlaze will
continue normal execution where it was paused.
Core O MicroBlaze is in pause mode after the
been set.
Core O Debug request that external logic should clear the
to allow debug access.
Core I Determines whether AXI accesses are non-secure or secure. The
default value is binary 0000, setting all interfaces to be secure.
Bit 0 =
Bit 1 =
Bit 2 =
Bit 3 =
Lockstep signals for high integrity applications. See
Core IO
for details.
Debug signals from MDM. See
Core IO
Core O Trace signals for real time HW analysis. See
= 2, for low-latency interrupt support.
.
= 1.
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Chapter 3: MicroBlaze Signal Interface Description
Description
C_DEBUG_ENABLED is set to 2
Wakeup signal, to allow debug access.
M_AXI_DP
M_AXI_IP
M_AXI_DC
M_AXI_IC
Table 3-15
SLEEP instruction
SUSPEND
Pause_Ack signal
Pause input signal has
Pause signal,
Table 3-13
for details.
Table 3-16 for details.
. However, if
Clk
must have
Clk
144
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