Xilinx MicroBlaze Reference Manual page 198

and Logical AND
rD, rA, rB
and
1 0 0 0 0 1
0
6
Description
The contents of register rA are ANDed with the contents of register rB; the result is placed into register
rD.
Pseudocode
← (rA) ∧ (rB)
(rD)
Registers Altered
• rD
Latency
1 cycle
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
16 21 31
199
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