Xilinx MicroBlaze Reference Manual page 223

Pseudocode
if E = 1 then
(rD)[0:31-IMM
(rD)[32-IMM
else if I = 1 then
←
mask (0xffffffff << (IMM
←
(rD) ((rA) << IMM
else if S = 1 then
←
(rD) (rA)
else if T = 1 then
≠
if IMM 0 then
(rD)[0:IMM-1]
(rD)[IMM:31]
else
←
(rD) (rA)
else
←
(rD) (rA)
Registers Altered
• rD
Latency
• 1 cycle with
• 2 cycles with
Notes
These are not Type B Instructions. There is no effect from a preceding imm instruction.
These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift
instructions (C_USE_BARREL=1).
The assembler code "bsifi rD, rA, width, shift" denotes the actual bit field width, not the IMM
which is computed by IMM
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
←
] 0
W
←
:31] (rA) >> IMM
W S
+ 1)) ⊕ (0xffffffff << IMM
W
) ∧ mask) ∨ ((rD) ∧ mask)
S
< <
IMM
←
(rA)[0]
← > >
(rA) IMM
> >
IMM
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
= shift + width - 1.
W
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Chapter 5: MicroBlaze Instruction Set Architecture
)
S
field,
W
224
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