Xilinx MicroBlaze Reference Manual page 162

Table 3-11: Big Endian Write Data Steering (Store from Register rD)
Address
[LSB-1:LSB]
11
10
01
00
10
00
00
Table 3-12: Little Endian Write Data Steering (Store from Register rD)
Address
[LSB-1:LSB]
11
10
01
00
10
00
00
Other masters could have more restrictive requirements for byte lane placement than those
Note:
allowed by MicroBlaze. Slave devices are typically attached "left-justified" with byte devices attached
to the most-significant byte lane, and halfword devices attached to the most significant halfword
lane. The MicroBlaze steering logic fully supports this attachment method.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Byte_Enable
Transfer Size
[0:3]
0001 byte
0010 byte
0100 byte
1000 byte
0011 halfword
1100 halfword
1111 word
Byte_Enable
Transfer Size
[0:3]
1000 byte
0100 byte
0010 byte
0001 byte
1100 halfword
0011 halfword
1111 word
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Chapter 3: MicroBlaze Signal Interface Description
Write Data Bus Bytes
Byte0 Byte1
rD[24:31]
rD[24:31]
rD[16:23] rD[24:31]
rD[0:7] rD[8:15]
Write Data Bus Bytes
Byte3 Byte2
rD[24:31]
rD[24:31]
rD[16:23] rD[24:31]
rD[0:7] rD[8:15]
Byte2 Byte3
rD[24:31]
rD[24:31]
rD[16:23] rD[24:31]
rD[16:23] rD[24:31]
Byte1 Byte0
rD[24:31]
rD[24:31]
rD[16:23] rD[24:31]
rD[16:23] rD[24:31]
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