Xilinx MicroBlaze Reference Manual page 252

Description
This instruction ensures that outstanding memory accesses on memory interfaces are
completed before any subsequent instructions are executed. This is necessary to guarantee
that self-modifying code is handled correctly, and that a DMA transfer can be safely started.
With self-modifying code, it is necessary to first use an MBAR instruction to wait for data
accesses, which can be done by setting IMM to 1, and then use another MBAR instruction to
clear the Branch Target Cache and empty the instruction prefetch buffer, which can be done
by setting IMM to 2.
To ensure that data to be read by a DMA unit has been written to memory, it is only
necessary to wait for data accesses, which can be done by setting IMM to 1.
When MicroBlaze is configured to use an MMU (
privileged when the most significant bit in IMM is set to 1. This means that if the instruction
is attempted in User Mode (
When the two most significant bits in IMM are set to 10 (
( ) and no exception occurs, MicroBlaze enters sleep mode after all outstanding
Suspend
accesses have been completed. and sets the
respectively to indicate this. The pipeline is halted, and MicroBlaze will not continue
execution until a bit in the
Pseudocode
if (IMM & 1) = 0 then
wait for instruction side memory accesses
if (IMM & 2) = 0 then
wait for data side memory accesses
←
PC PC + 4
if (IMM & 24)!= 0 then
enter sleep mode
Registers Altered
• PC
•
ESR[EC], in case a privileged instruction exception is generated
Latency
• 2 + N cycles when C_INTERCONNECT = 2 (AXI)
• 8 + N cycles when C_INTERCONNECT = 3 (ACE)
N is the number of cycles to wait for memory accesses to complete
Notes
This instruction must not be preceded by an imm instruction, and must not be placed in a delay slot.
The assembler pseudo-instructions sleep, hibernate, and suspend can be used instead of "mbar 16",
"mbar 8", and "mbar 24" respectively to enter sleep mode.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 5: MicroBlaze Instruction Set Architecture
C_USE_MMU
= 1) a Privileged Instruction exception occurs.
MSR[UM]
Sleep
input signal is asserted.
Wakeup
www.xilinx.com
>= 1) this instruction is
), 01 (
Sleep Hibernate
, or
Hibernate Suspend
Send Feedback
), or 11
output signal
253