Figure 5.2 Block Diagram Of Timebase Timer - Fujitsu F2MC-8L MB89620 Series Hardware Manual

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5. Block Diagram of Timebase Timer
The timebase timer consists of the following four blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
n Block Diagram of Timebase Timer
Timebase
timer counter
Divide-by
×2
-two F 1
C
Watchdog
timer clear
Power-on reset
Stop mode start
IRQA
timebase timer
interrupt
OF: Overflow
F : Source oscillation
C
Timebase timer counter
l
A 20-bit up-counter that uses the divide-by-two source oscillation as a count clock
l Counter clear circuit
In addition to being cleared by setting the TBTC register (TBR = "0"), the counter is cleared
when the device changes to stop mode (STBC: STP = "1") and by power-on reset (optional).
Interval timer selector
l
Selects one of four operating timebase timer counter bits as the interval timer bit. An overflow
on the selected bit triggers an interrupt.
TBTC register
l
The TBTC register is used to select the interval timer bit, clear the counter, control interrupts,
and check the state of the timebase timer.
MB89620 series
×2 ×2 ×2
2 7 10
. . . . . .
Counter
clear circuit
TBTC

Figure 5.2 Block Diagram of Timebase Timer

To A/D converter


To buzzer output

×2 ×2 ×2 ×2 ×2
11 12 13 14 15
OF
OF
OF
OF
Interval
timer selector
— — — TBIE TBOF TBR TBC1 TBC0
CHAPTER 5 TIMEBASE TIMER
To watchdog timer
×2 ×2 ×2 ×2 ×2
16 17 18 19 20
Clock controller for the
oscillation stabilization
delay time
(optional)
119