Samsung S5PC100 User Manual page 1425

VIDEO PROCESSOR
NOTE:
4.3.12 Video Processor Horizontal Offset of Source Image Control Register (VP_SRC_H_POSITION, R/W,
Address = 0xF010_ 0044)
VP_SRC_H_POSITION
Reserved
VP_SRC_H_POSITION
4.3.13 Video Processor Vertical Offset of Source Image Control Register (VP_SRC_V_POSITION, R/W,
Address = 0xF010_ 0048)
VP_SRC_V_POSITION
Reserved
9.8-16
Big Endian mode
63
Y0 Y1 Y2
Cb0 Cr0 Cb1
Little Endian mode
63
Y7 Y6 Y5
Cr3 Cb3 Cr2
Figure 9.8-6 Endian Mode
Bit
[31:15]
[14:0]
Bit
[31:10]
Y3 Y4 Y5
Cr1 Cb2 Cr2
Y4 Y3 Y2
Cb2 Cr1 Cb1
Description
Reserved, read as zero, do not modify
Horizontal offset in the source image
- (11.4) format
* For source image cropping,
VP_SRC_H_POSITION + VP_SRC_WIDTH
should be less than or equal to
VP_IMG_HSIZE_Y
* Note : (11.4) format means that
- '11' is a integer.
- '4' is a fraction.
Example) In case of H Position = 4
4(0x4(h) = 0100(b)) is integer. Because of 4bit
fraction, 0100(b) is had to do 4 time left shift
operation. As a result, register value is 4 * 2^4 =
64 = 0x40.
Description
Reserved, read as zero, do not modify
S5PC100 USER'S MANUAL (REV1.0)
0
Y6 Y7
Cb3 Cr3
0
Y1 Y0
Cr0 Cb0
Reset Value
0
0
Reset Value
0