Dedicated Prescaler Control Register (Sdcr) - Fujitsu F2MC-16LX Hardware Manual

20.2.3 Dedicated Prescaler Control Register (SDCR)

This section describes the configuration and functions of the dedicated prescaler
control register (SDCR).
I Dedicated prescaler control register (SDCR)
The bit configuration of the dedicated prescaler control register (SDCR) is illustrated below.
SDCR
address: 000029
00002D
The functions of the bits of the dedicated prescaler control register (SDCR) are described
below.
[Bit 15] MC: Machine clock device moDe select
This bit is used to enable operation of the communication prescaler.
0
1
[Bits 11, 10, 9, 8] DIV3, DIV2, DIV1, DIV0: DIVide3 to 0
These bits determine the division factor of the machine clocks.
DIV3 to 0
0000
0001
0010
0011
0100
0101
0110
0111
Note:
When changing the clock division factor, allow for a clock stabilization time of two clock
cycles before data transfer.
7 6 5
MD - -
H
H R/W - -
The communication prescaler stops.
The communication prescaler operates.
Division Ratio
Division by 1
B
Division by 2
B
Division by 3
B
Division by 4
B
Division by 5
B
Division by 6
B
Division by 7
B
Division by 8
B
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE
4 3 2 1
- DIV3 DIV2 DIV1 DIV0
- R/W R/W R/W R/W
0 Initial value
0---0000
B
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