Security Controller (Tzsc); Table 7. Peripheral Access Error Generation - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Global security controller (GTZC)

Secure privileged

Illegal S and P

Fail, illegal and event generated

1. Fail: All fetches from peripherals are rejected without ila generation.

Illegal: security infringement

S: ila_event due to illegal security infringement

P: ila_event due to illegal privileged infringement

S and P: ila_event due to secure and privileged infringement

Security controller (TZSC)

This block is composed of a configurable set of registers, providing the following features:

Control of secure and privileged protection for peripherals, done through the following

For watermark memory protection (internal memories), one privileged area can be

defined through GTZC_TZSC_MPCWMn_UPWMR, that defines the unprivileged area,

starting from the internal memory base address with a length defined through

GTZC_TZSC_MPCWMn_UPWMR.LGTH[11:0].

For watermark memory protection (internal memory), one privileged and unprivileged

read execute area can be defined through GTZC_TZSC_MPCWM1_UPWWMR, which

defines the unprivileged writable area, starting from the internal Flash memory base

unprivileged

SECCFGR1 register to control AHB/APB firewall stubs for the secure attribute of

all securable peripherals

PRIVCFGR1 register to control AHB/APB firewall stubs for the privileged attribute

of all securable peripherals

privileged peripheral

RM0453 Rev 1

unprivileged

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