ST STM32WL5 Series Reference Manual page 73

RM0453
Table 4. Memory map and peripheral register boundary addresses (continued)
Bus Boundary address
0x4260 0000 - 0x47FF FFFF
0x4240 0000 - 0x425F FFFF
0x4220 0000 - 0x423F FFFF
0x4200 0000 - 0x421F FFFF
AHB1
0x4002 3400 - 0x41FF FFFF
0x4002 3000 - 0x4002 33FF
0x4002 0C00 - 0x4002 2FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
0x4001 4C00 - 0x4001 FFFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 3C00 - 0x4001 43FF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
APB2
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 0400 - 0x4001 23FF
0x4001 0200 - 0x4001 03FF
0x4001 0100 - 0x4001 01FF
0x4001 0030 - 0x4001 00FF
0x4001 0000 - 0x4001 002F
Size
Peripheral
(bytes)
- Reserved
AHB1 bit banding
2048 K
(CPU1 only)
APB2 bit banding
2048 K
(CPU1 only)
APB1 bit banding
2048 K
(CPU1 only)
- Reserved
1 K CRC
- Reserved
1 K DMAMUX1
1 K DMA2
1 K DMA1
- Reserved
1 K TIM17
1 K TIM16
- Reserved
1 K USART1
- Reserved
1 K SPI1
1 K TIM1
- Reserved
1 K ADC
- Reserved
COMP
SYSCFG continue
1 K
VREFBUF
SYSCFG
RM0453 Rev 1
Peripheral register map
-
-
-
-
-
Section 17.4.6: CRC register map
-
Section 14.6.7: DMAMUX register map
Section 13.6.7: DMA register map
Section 13.6.7: DMA register map
-
Section 27.4.23: TIM16/TIM17 register
map
Section 27.4.23: TIM16/TIM17 register
map
-
Section 35.8.15: USART register map
-
Section 37.9.10: SPI/I2S register map
Section 25.4.30: TIM1 register map
-
Section 18.13: ADC register map
-
Section 21.6.3: COMP register map
Section 11.2.16: SYSCFG register map
Section 20.3.3: VREFBUF register map
Section 11.2.16: SYSCFG register map
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