Gtzc Tzsc Security Configuration Register (Gtzc_Tzsc_Seccfgr1) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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GTZC TZSC security configuration register

(GTZC_TZSC_SECCFGR1)

Address offset: 0x010

Reset value: 0x0000 0000

Secure write access only.

A bit of this register can be written only by a secure privileged transaction, when the

corresponding bit in GTZC_TZSC_PRIVCFGR1 is set to privileged. If unprivileged, the

Read access is authorized for any type of transaction, secure/non-secure,

privileged/unprivileged.

An illegal access event on a privileged access is only generated when all peripheral register

bits in GTZC_TZSC_PRIVCFGR1 are configured as privileged.

When TZSC configuration is locked in GTZC_TZSC_CR.LCK, this register can no longer be

When the system is non-secure (ESE = 0) this register cannot be written and is read zero.

Peripherals cannot be secured.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 PKASEC: Secure access mode enabled for PKA

Bits 12:4 Reserved, must be kept at reset value.

Bit 3 RNGSEC: Secure access mode enabled for RNG

Bit 2 AESSEC: Secure access mode enabled for AES

Bits 1:0 Reserved, must be kept at reset value.

0: Non-secure

0: Non-secure

0: Non-secure

RM0453 Rev 1

Global security controller (GTZC)

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