ST STM32WL5 Series Reference Manual page 43

RM0453
38.14.1 BPU control register (BPU_CTRLR) . . . . . . . . . . . . . . . . . . . . . . . . . 1440
38.14.2 BPU remap register (BPU_REMAPR) . . . . . . . . . . . . . . . . . . . . . . . . 1441
38.14.3 BPU comparator register x (BPU_COMPxR) . . . . . . . . . . . . . . . . . . 1441
38.14.4 BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . . . . 1442
38.14.5 BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . . . . 1443
38.14.6 BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . . . . 1443
38.14.7 BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . . . . 1444
38.14.8 BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . . . . 1444
38.14.9 BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . . . 1445
38.14.10 BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . . . . 1445
38.14.11 BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . . . 1446
38.14.12 BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . . . 1446
38.14.13 CPU2 BPU register map and reset values . . . . . . . . . . . . . . . . . . . . 1446
38.15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
39 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
39.1 Device electronic signature registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
39.1.1
39.1.2
39.1.3
39.1.4
40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
Unique device ID register (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
FLASH size data register (FLASHSIZE) . . . . . . . . . . . . . . . . . . . . . . 1450
Package data register (PKG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451
IEEE 64-bit unique device ID register (UID64) . . . . . . . . . . . . . . . . . 1451
RM0453 Rev 1
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