Flash Option Bytes; Option Bytes Description; Table 16. Option Bytes Organization - ST STM32WL5 Series Reference Manual

Embedded Flash memory (FLASH)
Programming and caches
If a Flash memory write access impacts data in the data cache, the Flash memory write
access modifies the data in the memory and in the cache.
If an erase operation in the Flash memory also concerns data in the data cache or
instruction cache, the user must ensure that these data are rewritten before they are
accessed during code execution. Upon an erase operation, the cache content is invalidated.
Note: The ICache and DCache must be flushed only when disabled (ICEN or DCEN = 0).
4.4

FLASH option bytes

4.4.1

Option bytes description

The option bytes can be read from the memory locations listed in the table below or from the
following option byte registers:
•
FLASH option register (FLASH_OPTR)
•
FLASH PCROP zone A start address register (FLASH_PCROP1ASR)
•
FLASH PCROP zone A end address register (FLASH_PCROP1AER)
•
FLASH PCROP zone B start address register (FLASH_PCROP1BSR)
•
FLASH PCROP zone B end address register (FLASH_PCROP1BER)
•
FLASH WRP area A address register (FLASH_WRP1AR)
• FLASH WRP area B address register (FLASH_WRP1BR)
•
FLASH IPCC mailbox data buffer address register (FLASH_IPCCBR)
• FLASH CPU2 access control register (FLASH_C2ACR)
•
FLASH secure SRAM start address and CPU2 reset vector register (FLASH_SRRVR)
(1)
Address
0x1FFF 7800
0x1FFF 7808
0x1FFF 7810
0x1FFF 7818
0x1FFF 7820
0x1FFF 7828
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Table 16. Option bytes organization

WRP1A_END[6:0]
WRP1B_END[6:0]
RM0453 Rev 1
RM0453
RDP[7:0]
PCROP1A_STRT[7:0]
PCROP1A_END[7:0]
WRP1A_STRT[6:0]
WRP1B_STRT[6:0]
PCROP1B_STRT[7:0]