S4, S5: Dma-Bus; Boot Configuration; Table 1. Device Boot Mode - ST STM32WL5 Series Reference Manual

Memory and bus architecture
SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2
peripherals and the AHB3 peripherals including the APB3 peripherals.
2.1.5

S4, S5: DMA-bus

These buses connect the AHB master interface of the DMAs to the bus matrix.The targets of
this bus are the internal Flash memory, SRAM1, SRAM2 the AHB1 peripherals including the
APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the
APB3 peripherals.
AHB/APB bridges
The two bridges AHB to APB1 and AHB to ABP2 provide full synchronous connections
between the AHB1 and the two APB buses, allowing flexible selection of the peripheral
frequency.
The bridge AHB to APB3 provides full synchronous connections between the AHB and the
APB bus, allowing flexible selection of the frequency between the AHB and peripherals.
Refer to
mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled, except for the SRAM1/2 and the
Flash memory interface. Before using a peripheral, its clock must be enabled in the
RCC_AHBxENR and RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
2.2

Boot configuration

Three different CPU1 boot modes and one CPU2 boot mode can be selected through the
BOOT0 pin and nBOOT1 bit in the user options.
Boot is furthermore conditioned by the CPU1 boot lock enable, CPU2 boot lock enable and
the user Flash memory empty check, as shown in the table below.
Boot mode selection
0
x x X
1
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Section 2.6.2: Memory map and register boundary addresses

Table 1. Device boot mode

x x No
CPU1 aliasing space
Hold
x
SRAM1 boot
RM0453 Rev 1
RM0453
for the address
CPU2 boot
(1)(2)(3)
SFI/RSS boot
Hold