B2.103 Vtcr_El2, Virtualization Translation Control Register, El2 - ARM Cortex-A76 Core Technical Reference Manual

B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2

The VTCR_EL2 controls the translation table walks required for the stage 2 translation of memory
accesses from Non-secure EL0 and EL1.
It also holds cacheability and shareability information for the accesses.
Bit field descriptions
VTCR_EL2 is a 32-bit register, and is part of:
• The Virtualization registers functional group.
• The Virtual memory control registers functional group.
Bits[28:25] and bits[22:21], architecturally defined, are implemented in the core.
TG0, [15:14]
Configurations
100798_0300_00_en
31 30 29 28 27 26 25 24 23 22 21 20 19
HWU62
HWU61
HWU60
HWU59
1
RES
0
RES
Note
TTBR0_EL2 granule size. The possible values are:
4KB.
00
64KB.
01
16KB.
10
Reserved.
11
All other values are not supported.
RW fields in this register reset to architecturally
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
®
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2
18 16 15 14
PS TG0
HD
HA
VS
Figure B2-86 VTCR_EL2 bit assignments
UNKNOWN
reserved.
Non-Confidential
B2 AArch64 system registers
13 12 11 10 9 8 7 6 5
SH0 SL0
IRGN0
ORGN0
values.
0
T0SZ
B2-288