ARM Cortex-A76 Core Technical Reference Manual page 433

Chapter D4
AArch32 PMU registers
This chapter describes the AArch32 PMU registers and shows examples of how to use them.
It contains the following sections:
• D4.1 AArch32 PMU register summary on page
• D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0 on page
• D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1 on page
• D4.4 PMCR, Performance Monitors Control Register on page
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