D3.1 Memory-Mapped Debug Register Summary - ARM Cortex-A76 Core Technical Reference Manual

D3.1 Memory-mapped debug register summary
The following table shows the offset address for the registers that are accessible from the external debug
interface.
For those registers not described in this chapter, see the Arm
Armv8-A architecture profile.
Offset Name
0x000-0x01C -
0x020
EDESR
0x024
EDECR
0x028-0x02C -
0x030
EDWAR[31:0]
0x034
EDWAR[63:32]
0x038-0x07C -
0x080
DBGDTRRX_EL0
0x084
EDITR
0x088 EDSCR
0x08C
DBGDTRTX_EL0
0x090
EDRCR
0x094
EDACR
0x098
EDECCR
0x09C
-
0x0A0
-
0x0A4
-
0x0A8
-
0x0AC
-
0x0B0-0x2FC -
0x300
OSLAR_EL1
0x304-0x30C -
0x310
EDPRCR
0x314
EDPRSR
0x318-0x3FC -
0x400
DBGBVR0_EL1[31:0]
0x404
DBGBVR0_EL1[63:32]
100798_0300_00_en
Type Width Description
- - Reserved
RW 32 External Debug Event Status Register
RW 32 External Debug Execution Control Register
- - Reserved
RO 64 External Debug Watchpoint Address Register
- - Reserved
RW 32 Debug Data Transfer Register, Receive
WO 32 External Debug Instruction Transfer Register
RW 32
External Debug Status and Control Register
WO 32 Debug Data Transfer Register, Transmit
WO 32 D3.14 EDRCR, External Debug Reserve Control Register
on page D3-432
RW 32 Reserved
RW 32 External Debug Exception Catch Control Register
- - Reserved
- -
Reserved
- - Reserved
- - Reserved
- -
Reserved
- - Reserved
WO 32 OS Lock Access Register
- - Reserved
RW 32 External Debug Power/Reset Control Register
RO 32
External Debug Processor Status Register
- - Reserved
RW 64 Debug Breakpoint Value Register 0
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
D3 Memory-mapped debug registers

D3.1 Memory-mapped debug register summary

Architecture Reference Manual Armv8, for
®
Table D3-1 Memory-mapped debug register summary
D3-416