B2.92 Sctlr_El3, System Control Register, El3 - ARM Cortex-A76 Core Technical Reference Manual

B2.92 SCTLR_EL3, System Control Register, EL3
The SCTLR_EL3 provides top-level control of the system, including its memory system at EL3.
Bit field descriptions
SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.
This register resets to
RES0, [31:30]
RES1, [29:28]
RES0, [27:26]
EE, [25]
I, [12]
C, [2]
M, [0]
100798_0300_00_en
.
0x30C50838
31 30 29 28 27 26 25 24 23 22 21
EE IESB
1
RES
0
RES
Reserved.
RES0
Reserved.
RES1
Reserved.
RES0
Exception endianness. This bit controls the endianness for:
• Explicit data accesses at EL3.
• Stage 1 translation table walks at EL3.
The possible values are:
Little endian.
0
Big endian.
1
The reset value is determined by the CFGEND configuration signal.
Global instruction cache enable. The possible values are:
Instruction caches disabled. This is the reset value.
0
Instruction caches enabled.
1
Global enable for data and unifies caches. The possible values are:
Disables data and unified caches. This is the reset value.
0
Enables data and unified caches.
1
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B2.92 SCTLR_EL3, System Control Register, EL3

20 19 18 17 16 15 14 13
WXN
Figure B2-76 SCTLR_EL3 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
12 11 10 6 5 4 3
I
2 1 0
C A M
SA
B2-276