B4.7 Icc_Ctlr_El1, Interrupt Controller Control Register, El1 - ARM Cortex-A76 Core Technical Reference Manual

B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
ICC_CTLR_EL1 controls aspects of the behavior of the GIC CPU interface and provides information
about the features implemented.
Bit field descriptions
ICC_CTLR_EL1 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The GIC control registers functional group.
31
RES
RES0, [31:16]
A3V, [15]
SEIS, [14]
IDbits, [13:11]
PRIbits, [10:8]
RES0, [7]
PMHE, [6]
100798_0300_00_en
0
Reserved, .
RES0
Affinity 3 Valid. The value is:
The CPU interface logic supports non-zero values of Affinity 3 in SGI generation
1
System registers.
SEI Support. The value is:
The CPU interface logic does not support local generation of SEIs.
0
Identifier bits. The value is:
The number of physical interrupt identifier bits supported is 16 bits.
0
This field is an alias of ICC_CTLR_EL3.IDbits.
Priority bits. The value is:
The core supports 32 levels of physical priority with 5 priority bits.
0x4
Reserved, .
RES0
Priority Mask Hint Enable. This bit is read only and is an alias of ICC_CTLR_EL3.PMHE. The
possible values are:
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B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1

16 15 14 13 11 10
IDbits PRIbits
Figure B4-3 ICC_CTLR_EL1 bit assignments
reserved.
Non-Confidential
B4 GIC registers
8 7 6 5 2 1 0
CBPR
EOImode
PMHE
SEIS
A3V
B4-319