D9.61 Trcrsctlrn, Resource Selection Control Registers 2-16 - ARM Cortex-A76 Core Technical Reference Manual

D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
The TRCRSCTLRn controls the trace resources. There are eight resource pairs, the first pair is
predefined as {0,1,pair=0} and having reserved select registers. This leaves seven pairs to be
implemented as programmable selectors.
Bit field descriptions
The TRCRSCTLRn is a 32-bit register.
RES0, [31:22]
PAIRINV, [21]
INV, [20]
RES0, [19]
GROUP, [18:16]
RES0, [15:8]
SELECT, [7:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCRSCTLRn can be accessed through the external debug interface, offset
100798_0300_00_en
31
PAIRINV
0
RES
Reserved.
RES0
Inverts the result of a combined pair of resources.
This bit is implemented only on the lower register for a pair of resource selectors.
Inverts the selected resources:
Resource is not inverted.
0
Resource is inverted.
1
Reserved.
RES0
Selects a group of resources. See the Arm
information.
Reserved.
RES0
Selects one or more resources from the required group. One bit is provided for each resource
from the group.
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D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16

22 21 20 19 18 16 15
GROUP
INV
Figure D9-58 TRCRSCTLRn bit assignments
ETM Architecture Specification, ETMv4 for more
®
reserved.
Non-Confidential
D9 ETM registers
8 7 0
SELECT
®
.
0x208-0x023C
D9-571