B3.10 Err0Status, Error Record Primary Status Register - ARM Cortex-A76 Core Technical Reference Manual

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B3.10
ERR0STATUS, Error Record Primary Status Register
The ERR0STATUS contains information about the error record:
Whether any error has been detected.
Whether any detected error was not corrected and returned to a master.
Whether any detected error was not corrected and deferred.
Whether a second error of the same type was detected before software handled the first error.
Whether any error has been reported.
Whether the other error record registers contain valid information.
Bit field descriptions
ERR0STATUS is a 32-bit register.
AV
UE
ER
OF
MV
AV, [31]
V, [30]
UE, [29]
ER, [28]
100798_0300_00_en
31 30
29
28 27 26 25 24 23 22 21 20 19
CE
V
0
RES
Address Valid. The possible values are:
ERR0ADDR is not valid.
0
ERR0ADDR contains an address associated with the highest priority error recorded by this
1
record.
Status Register valid. The possible values are:
ERR0STATUS is not valid.
0
ERR0STATUS is valid. At least one error has been recorded.
1
Uncorrected error. The possible values are:
No error that could not be corrected or deferred has been detected.
0
At least one error that could not be corrected or deferred has been detected. If error recovery
1
interrupts are enabled, then the interrupt signal is asserted until this bit is cleared.
Error reported. The possible values are:
No external abort has been reported.
0
The node has reported an external abort to the master that is in access or making a
1
transaction.
Copyright © 2016–2018 Arm Limited or its affiliates. All rights

B3.10 ERR0STATUS, Error Record Primary Status Register

UET
PN
DE
Figure B3-8 ERR0STATUS bit assignments
reserved.
Non-Confidential
B3 Error system registers
5
4
0
SERR
B3-307

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