Chapter B2; Aarch64 System Registers - ARM Cortex-A76 Core Technical Reference Manual

Chapter B2

AArch64 system registers

This chapter describes the system registers in the AArch64 state.
It contains the following sections:
• B2.1 AArch64 registers on page
• B2.2 AArch64 architectural system register summary on page
• B2.3 AArch64 implementation defined register summary on page
• B2.4 AArch64 registers by functional group on page
• B2.5 ACTLR_EL1, Auxiliary Control Register, EL1 on page
• B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 on page
• B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 on page
• B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1 on page
• B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 on page
• B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 on page
• B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1 on page
• B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 on page
• B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 on page
• B2.14 AIDR_EL1, Auxiliary ID Register, EL1 on page
• B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 on page
• B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 on page
• B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 on page
• B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 on page
• B2.19 CLIDR_EL1, Cache Level ID Register, EL1 on page
• B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1 on page
• B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 on page
• B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 on page
• B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 on page
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