ARM Cortex-A76 Core Technical Reference Manual page 443

D4 AArch32 PMU registers
D4.4 PMCR, Performance Monitors Control Register
Configurations
AArch32 System register PMCR is architecturally mapped to AArch64 System register
PMCR_EL0. See D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
on page D5-453.
AArch32 System register PMCR bits [6:0] are architecturally mapped to External register
PMCR_EL0[6:0].
There is one instance of this register that is used in both Secure and Non-secure states.
This register is in the Warm reset domain. Some or all RW fields of this register have defined
reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level
that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to
architecturally values.
UNKNOWN
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