B2.70 Id_Isar5_El1, Aarch32 Instruction Set Attribute Register 5, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
The ID_ISAR5_EL1 provides information about the instruction sets that the core implements.
Bit field descriptions
ID_ISAR5_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
[31:28]
RDM, [27:24]
[23:20]
CRC32, [19:16]
SHA2, [15:12]
SHA1, [11:8]
AES, [7:4]
100798_0300_00_en
31 28 27 24 23
RDM
0
RES
Reserved.
RES0
VQRDMLAH and VQRDMLSH instructions in AArch32. The value is:
VQRDMLAH and VQRDMLSH instructions are implemented.
0x1
Reserved.
RES0
Indicates whether CRC32 instructions are implemented in AArch32 state. The value is:
, ,
0x1 CRC32B CRC32H CRC32W
implemented.
Indicates whether SHA2 instructions are implemented in AArch32 state. The possible values
are:
No SHA2 instructions implemented. This is the value when the Cryptographic
0x0
Extensions are not implemented or are disabled.
,
0x1 SHA256H SHA256H2
the value when the Cryptographic Extensions are implemented and enabled.
Indicates whether SHA1 instructions are implemented in AArch32 state. The possible values
are:
No SHA1 instructions implemented. This is the value when the Cryptographic
0x0
Extensions are not implemented or are disabled.
, ,
0x1 SHA1C SHA1P SHA1M
This is the value when the Cryptographic Extensions are implemented and enabled.
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B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

20 19 16 15
CRC32 SHA2
Figure B2-54 ID_ISAR5_EL1 bit assignments
, , , and
CRC32CB CRC32CH
, , and
SHA256SU0 SHA256SU1
, , , and
SHA1H SHA1SU0 SHA1SU1
reserved.
Non-Confidential
B2 AArch64 system registers
12 11 8 7 4 3
SHA1 AES
instructions are
CRC32CW
instructions are implemented. This is
instructions are implemented.
0
SEVL
B2-243