D7.7 Pmccntsr, Pmu Cycle Counter Snapshot Register - ARM Cortex-A76 Core Technical Reference Manual

D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register
The PMCCNTSR is a captured copy of PMCCNTR_EL0.
Once it is captured, the value in PMCCNTSR is unaffected by writes to PMCCNTR_EL0 and
PMCR_EL0.C.
Configurations
There are no configuration notes.
Usage constraints
Any access to PMCCNTSR returns an error if any of the following occurs:
• The core power domain is off.
• DoubleLockStatus() == TRUE.
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D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register

D7 PMU snapshot registers
D7-478