D9.73 Trcviiectlr, Viewinst Include-Exclude Control Register - ARM Cortex-A76 Core Technical Reference Manual

D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
The TRCVIIECTLR defines the address range comparators that control the ViewInst Include/Exclude
control.
Bit field descriptions
The TRCVIIECTLR is a 32-bit register.
RES0, [31:20]
EXCLUDE, [19:16]
RES0, [15:4]
INCLUDE, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCVIIECTLR can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Defines the address range comparators for ViewInst exclude control. One bit is provided for
each implemented Address Range Comparator.
Reserved.
RES0
Defines the address range comparators for ViewInst include control.
Selecting no include comparators indicates that all instructions must be included. The exclude
control indicates which ranges must be excluded.
One bit is provided for each implemented Address Range Comparator.
Copyright © 2016–2018 Arm Limited or its affiliates. All rights

D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register

20 19 16 15
EXCLUDE
Figure D9-70 TRCVIIECTLR bit assignments
reserved.
Non-Confidential
D9 ETM registers
4 3 0
INCLUDE
®
.
0x084
D9-585