D9.56 Trcpidr2, Etm Peripheral Identification Register 2 - ARM Cortex-A76 Core Technical Reference Manual

D9.56 TRCPIDR2, ETM Peripheral Identification Register 2
The TRCPIDR2 provides information to identify a trace component.
Bit field descriptions
The TRCPIDR2 is a 32-bit register.
RES0, [31:8]
Revision, [7:4]
JEDEC, [3]
DES_1, [2:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCPIDR2 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
ETM revision.
0x0
. Indicates a JEP106 identity code is used.
0b1
RES1
Arm Limited. This is bits[6:4] of JEP106 ID code.
0b011
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D9.56 TRCPIDR2, ETM Peripheral Identification Register 2

Figure D9-54 TRCPIDR2 bit assignments
reserved.
Non-Confidential
D9 ETM registers
8 7 4 3 2 0
Revision DES_1
JEDEC
®
.
0xFE8
D9-566