ARM Cortex-A76 Core Technical Reference Manual page 247

Configurations
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
100798_0300_00_en
Support for:
0x5
• VMSAv7, with support for remapping and the Access flag.
• The PXN bit in the Short-descriptor translation table format descriptors.
• The Long-descriptor translation table format.
Must be interpreted with ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, and
ID_MMFR4_EL1. See:
• B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1 on page
• B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1 on page
• B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 on page
• B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page
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B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
reserved.
Non-Confidential
B2 AArch64 system registers
B2-248.
B2-250.
B2-252.
B2-254.
®
B2-247