D9.34 Trcidr5, Id Register 5 - ARM Cortex-A76 Core Technical Reference Manual

D9.34 TRCIDR5, ID Register 5
The TRCIDR5 returns how many resources the trace unit supports.
Bit field descriptions
REDFUNCNTR, [31]
NUMCNTR, [30:28]
NUMSEQSTATE, [27:25]
RES0, [24]
LPOVERRIDE, [23]
ATBTRIG, [22]
TRACEIDSIZE, [21:16]
RES0, [15:12]
NUMEXTINSEL, [11:9]
100798_0300_00_en
31 30 28 27 25 24 23 22 21
0
RES
Reduced Function Counter implemented:
Reduced Function Counter not implemented.
0
Number of counters implemented:
Two counters implemented.
0b010
Number of sequencer states implemented:
Four sequencer states implemented.
0b100
Reserved.
RES0
Low-power state override support:
Low-power state override support implemented.
1
ATB trigger support:
ATB trigger support implemented.
1
Number of bits of trace ID:
Seven-bit trace ID implemented.
0x07
Reserved.
RES0
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
16 15
TRACEIDSIZE
ATBTRIG
LPOVERRIDE
NUMSEQSTATE
NUMCNTR
REDFUNCNTR
Figure D9-32 TRCIDR5 bit assignments
reserved.
Non-Confidential
D9 ETM registers

D9.34 TRCIDR5, ID Register 5

12 11 9 8
NUMEXTIN
NUMEXTINSEL
0
D9-543