B3.8 Err0Pfgctlr, Error Pseudo Fault Generation Control Register - ARM Cortex-A76 Core Technical Reference Manual

B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
The ERR0PFGCTLR is the Cortex-A76 node register that enables controlled fault generation.
Bit field descriptions
ERR0PFGCTLR is a 32-bit read/write register.
CDNEN, [31]
R, [30]
[29:7]
CE, [6]
DE, [5]
100798_0300_00_en
31 30 29
R
CDNEN
0
RES
Count down enable. This bit controls transfers from the value that is held in the
ERR0PFGCDNR into the Error Generation Counter and enables this counter to start counting
down. The possible values are:
The Error Generation Counter is disabled.
0
The value that is held in the ERR0PFGCDNR register is transferred into the
1
Error Generation Counter. The Error Generation Counter counts down.
Restartable bit. When it reaches 0, the Error Generation Counter restarts from the
ERR0PFGCDNR value or stops. The possible values are:
When it reaches 0, the counter stops.
0
When it reaches 0, the counter reloads the value that is stored in ERR0PFGCDNR
1
and starts counting down again.
Reserved, .
RES0
Corrected error generation enable. The possible values are:
No corrected error is generated.
0
A corrected error might be generated when the Error Generation Counter is
1
triggered.
Deferred Error generation enable. The possible values are:
No deferred error is generated.
0
A deferred error might be generated when the Error Generation Counter is
1
triggered.
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B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register

Figure B3-6 ERR0PFGCTLR bit assignments
reserved.
Non-Confidential
B3 Error system registers
7 6 5 4 2 1 0
CE
DE
UC
B3-303